The present invention relates to a process for the manufacture of a power MOSFET semiconductor device and, more specifically, relates to a novel process for the manufacture of such devices in a float zone (non-epi) monocrystalline silicon substrate.
Power MOSFETs are well known in the art and include such devices as shown in U.S. Pat. No. 5,008,725, the subject matter of which is incorporated herein by reference. Such devices are manufactured and sold by the International Rectifier Corporation of El Segundo, Calif. under the Registered Trademark xe2x80x9cHEXFETxe2x80x9d.
Power MOSFETs are typically vertical conduction devices, namely devices in which the semiconductor substrate is part of the conduction path of the device. To reduce the on-resistance in the conduction path, a heavily doped semiconductor substrate of monocrystalline silicon is usually used. The junctions which form the channel and source regions, however, are not readily formed in such heavily doped material. Therefore, a thin lower concentration epitaxial layer is provided on the top surface of the substrate, and all junctions are formed in the epitaxial layer. The added epitaxial layer substantially increases the cost of the starting wafer material and thus the cost of the device.
It is known that semiconductor devices such as IGBTs and diodes can be made in float zone (non-epi) material as disclosed in the above mentioned related applications and as described, for example, in the paper entitled xe2x80x9cNPT-IGBT-Optimizing for Manufacturabilityxe2x80x9d by Burns et al., 0-7803-3106-0/9655.00 1996 IEEE, pages 331 to 334. In that paper, a typical D-MOS type structure is formed in the top surface of an Nxe2x88x92 float zone wafer and a boron implant is applied to the back side of the wafer. This is followed by an aluminum collector contact, used in place of a laser activation anneal of the boron implanted P region to avoid a high temperature anneal step which would adversely affect the DMOS structure on the top surface. Note that if aluminum only is added to the back surface, without the boron implant, that the aluminum will produce a P type region, again producing an IGBT type device.
If a MOSFET is to be made in Nxe2x88x92 float zone material, it is necessary to form an N+ back contact region without inadvertently forming a P type region and without a high temperature activation anneal of an N type implant which would adversely affect the top wafer structure.
It is therefore desirable to provide a manufacturing process in which the junctions are formed in a lightly doped semiconductor substrate that is without an epitaxial layer but which does not have significantly increased on-resistance.
In accordance with the present invention, a lightly doped, Nxe2x88x92 float zone wafer is provided as the semiconductor substrate. Junction regions such as a typical D-MOS structure that form a vertical conduction MOSFET are formed in the top surface of the monocrystalline wafer substrate using high temperature processes known in the art. Then, to reduce the on-resistance, the back surface of the wafer is ground to reduce the thickness of the substrate. A protective layer may be deposited on the top surface prior to grinding. Subsequently, the back surface of the wafer receives a shallow (500 xc3x85) ion implant dose of phosphorus or other N type dopant species, to provide a good ohmic drain contact region.
The implanted dopant is then only partially activated by a low temperature anneal to prevent affecting the D-MOS junction in the top surface. When using a laser anneal, most of the laser energy is absorbed in the thin N+ implant and it melts and regrows with maximum activation. Alternatively, a xe2x80x9ctransparentxe2x80x9d cathode region can be formed on the back surface using very highly doped N type amorphous silicon layer in place of the ion implant. A backside contact electrode is then formed preferably with titanium silicide and titanium or other metals. Aluminum is not used to avoid the creation of a P type region.
Advantageously, the vertical conduction device is formed without an epitaxial silicon layer so that the cost of the starting material is significantly reduced. The junctions, however, are formed in a lightly doped silicon substrate and the top surface of the wafer is processed using known processing steps. Moreover, the grinding of the back surface of the wafer reduces the conduction path through the substrate, which reduces the resistance of the device. The grind also creates a polycrystalline silicon structure in the back of the wafer which is helpful for later forming the metal silicide layer. Further, the partially activated dopant species that is implanted into the back surface or the xe2x80x9ctransparentxe2x80x9d cathode provides a good ohmic contact with the back contact electrode.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.